RobosoftSystems - Educational Robotics - Engineering Workshops - Verilog workshop

VLSI : Verilog Workshop

This comprehensive workshop is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioural source code. This workshop addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This workshop combines insightful lecture with practical lab exercises to reinforce key concepts.

Workshop Duration

Its a 2 days workshop. In this two-day workshop, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Who Should Attend?

Engineering students who want to use Verilog effectively for modelling, design, and synthesis of digital designs. This knowledge can be used for designing VLSI based projects for final year.

Prerequisites

• Basic digital design knowledge

Software Tools

• Xilinx ISE™ 9.2i
• Mentor Graphics Modelsim Simulator

Skills Gained

After completing this Workshop, you will be able to:

• Write RTL Verilog code for synthesis
• Create Finite State Machines (FSMs) by using Verilog
• Target and optimize Xilinx FPGAs by using Verilog
• Create and manage designs within the ISE software design environment

Registration Details

Participants have to register online . Charges for the workshop are Rs 2500/- per student (applicable taxes extra).

This cost includes:-

• Cost of the training program
• Cost of utility CD
• Cost of Certificate

>>Verilog Workshop Outline Details